Digital guide
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GE IC693CPU372-AB
Single-slot Embedded Ethernet CPU module for GE Series 90-30 PLC systems (revision AB). It combines a 32-bit processor with a dual-port Ethernet switch for high-speed PLC-to-PLC communication.
- Technical Specifications: AMD SC520 32-bit RISC processor @ 133 MHz; 120 KB configurable user memory (firmware 9.0+); 0.15 ms/1K Boolean scan speed; 4096 discrete I/O points (2048 in / 2048 out); up to 2048 analog inputs / 512 analog outputs (128–32,640 words configurable); two 10/100Base-T/TX auto-sensing RJ-45 ports with internal switch (shared IP, daisy-chain capable); 1.4 A @ 5 VDC (7.4 W); 0–60 °C operating; single-slot Series 90-30 rack format; built-in HTTP web server.
Detailed content
- Supported Protocols: EGD (Ethernet Global Data), SRTP, Modbus/TCP Client-Server, SNP/SNPX slave.
- Functional Features: Dual-processor architecture — AMD SC520 handles protocol stack while main CPU executes user logic; both share backplane data registers for seamless I/O mapping; embedded two-port Ethernet switch eliminates external switching hardware; web server runs independently of PLC scan, enabling remote configuration without impacting real-time control; galvanic isolation between Ethernet and backplane prevents ground loops.
- Application Scenarios: Large-scale water treatment plants with multiple pump stations and centralized SCADA; material handling conveyor networks requiring high-speed PLC coordination and DLR topology; process plants needing Modbus/TCP integration with third-party DCS/SCADA.
- Expansion & Architecture: Occupies Slot 1 on the Series 90-30 backplane; supports up to 7 expansion/remote baseplates (1 CPU + 7 expansion); firmware CPU 12.15–12.71, Ethernet 4.50–6.20 (varies by revision).
- Installation & Usage Notes: Requires high-capacity 5 VDC power supply (standard Series 90-30 supplies may be insufficient); frame ground connection at CPU slot is mandatory for EMC compliance; on power-up, CPU self-test takes 5–8 s followed by Ethernet boot 2–3 s — both EOK and LAN LEDs must be solid before normal operation; supports Device Level Ring (DLR) redundancy for single-point-of-failure elimination.
