Triple Modular Redundant (TMR) architecture

5 VDC logic, ~12 W

Proprietary Mark IV backplane bus

Features:​ Voted I/O, watchdog per lane, EEPROM config store, on-board serial debug.

Materials & Structure:​ 8-layer FR-4, metal bracket, DIP sockets for EPROM, three identical lanes on one board.

Working Principle:​ Each lane reads inputs, computes control law, votes outputs with other lanes; mismatch forces corrective trip to safe state.

Installation:​ Seat in Mark IV control cubicle slot A1; burn identical EPROM set across lanes; label lane cables.

Precautions:​ Do not mix firmware revisions across lanes; backup EEPROM image; handle by edges only.