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Densan DVE-SH7604 (9271)

Product Introduction
The Densan DVE-SH7604 (9271) is a Densan carrier board built around the Hitachi/Renesas SH7604 32-bit RISC single-chip microcontroller based on the SuperH architecture. The SH7604 integrates a CPU core, cache, 32-bit multiplier, divide unit, direct memory access controller (DMAC), timers, serial communication interface (SCI), interrupt controller (INTC), and bus state controller. On the Densan carrier board, the SH7604 serves as the main embedded processor for real-time control, communication management, and VME/industrial I/O orchestration.

Detailed content

Technical Specifications
The SH7604 microprocessor operates as a 32-bit RISC device with a maximum clock frequency of 28.7 MHz and is packaged in a 144-pin PQFP (Plastic Quad Flat Package). It supports a serial communication interface (SCI) that handles both asynchronous and clocked synchronous serial communication, along with a multiprocessor communication function for serial communication among two or more processors. The device includes two internal bus masters—the CPU and the DMAC. When synchronous DRAM, DRAM, or pseudo-SRAM is connected and refresh control is being performed, the refresh request becomes a third bus master. The SH7604 also provides a DRAM interface function that allows direct connection to DRAM, supporting burst read single write operations with a CAS latency of 1 to 3, a sequential wrap type, and a burst length of 8 or 4 depending on whether the bus width is 16 bits or 32 bits.

Functional Features
The SH7604 incorporates a 32-bit multiplier capable of performing high-speed sum-of-product (multiply-and-accumulate) operations. The device also features a bus arbitration function that releases the bus to an external device after the bus cycle being executed is completed when a bus release request is received. Because the CPU is connected to cache memory by a dedicated internal bus, cache memory can be read even when the bus is being used by another bus master on the chip or externally. The SH7604 normally uses big-endian alignment for data input and output but provides an endian conversion function for the CS2 space to enable connection to little-endian devices. The CS3 space can become pseudo-SRAM space, allowing the pseudo-SRAM interface function to directly connect the SH7604 to pseudo-SRAM with an interface data width of 16 or 32 bits.

Application Scenarios
The Densan DVE-SH7604 (9271) is deployed as an embedded controller board for real-time control, communication management, and VME/industrial I/O orchestration. It is suitable for industrial automation, factory automation equipment, and embedded VME systems that require a compact, integrated 32-bit RISC processing platform with on-chip peripherals and direct memory interface capabilities.

Material Composition
The board is constructed as a printed circuit board assembly populated with the SH7604 microcontroller and associated support components. Specific PCB material composition and layer stack-up details are not published in public documentation.

Structural Characteristics
The Densan DVE-SH7604 (9271) is a VME-class embedded controller board. The 9271 suffix identifies a specific board revision or configuration within the Densan DVE product family. The board integrates the SH7604 RISC microprocessor as the central processing element.

Working Principle
The SH7604 processor executes 32-bit RISC instructions from the SuperH instruction set. The integrated bus state controller manages external memory access, including synchronous DRAM, DRAM, and pseudo-SRAM interfaces. The DMAC handles data transfers between memory and peripherals without CPU intervention. The SCI provides serial communication channels for maintenance and data exchange. The interrupt controller manages prioritized interrupt requests from on-chip and external sources.

Installation Requirements
The board is designed for installation in VMEbus chassis systems. The SH7604 requires proper power-on sequencing when synchronous DRAM is used—the mode must first be set after the power is turned on to properly initialize the synchronous DRAM. When DRAM is used after power-on, there is a waiting period during which accesses cannot be performed. Board-level I/O assignment, connector pinout, and mechanical mounting specifications must be confirmed from the official Densan manual.

Usage Precautions
The SH7604 does not support little-endian mode for devices with an 8-bit data bus width. The endian conversion function is limited to the CS2 space. Refresh control must be properly configured when using synchronous DRAM, DRAM, or pseudo-SRAM. The device should not be operated outside its specified voltage and temperature ranges. Any board-level configuration or firmware changes must be verified against the official Densan release documentation.

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